module frequency_1Hz(
	input clk_51200Hz,
	input rst_n,
	output reg clk_1Hz		//51.2K / 1 = 51200; 51200 / 2 - 1 = 25_599
);

	reg[14:0] count;
	
	always @(posedge clk_51200Hz or negedge rst_n) begin
		if(rst_n == 1'b0) begin
			count = 15'b0;
			clk_1Hz = 1'b0;
		end
		else begin
			if(count == 15'd25_59) begin
				clk_1Hz = ~clk_1Hz;
				count = 15'd0;
			end
			else begin
				count = count + 15'd1;
			end
		end
	end

endmodule
